CHIPS Alliance
Open source IP, tools & standards for ASIC/FPGA

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fpgachiselrisc-vsystemverilogASIC

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socIP coresASIC designHDLchiplets
Past Projects
Support Zvk in T1 (RISC-V Vector coprocessor)
Syed Hassan Ul Haq
Our "Support Zvk in T1" project aims to upgrade the T1 processor by adding Zvk, a cryptographic feature from the RISC-V architecture, enhancing its...
Create a GDS reader/writer in OpenROAD
Muddassir Ali Siddiqui
I, Muddassir Ali, a final-year Computer Systems Engineering undergraduate student from Pakistan, aim to contribute to the OpenROAD project by...
Relational Framework for Prompt-based Automatic Layout Generation with Glayout
Chetanya Goyal
The proposal seeks to build upon an existing relational framework that facilitates the generation of DRC-compliant analog layouts through...
GDS Reader/Writer in OpenROAD
Fangzhong (Barry) Lyu
This Project adds GDS input and output features to OpenRoad. It would replace the current GDS manipulation scheme, which is through Klayout, and...