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Open source IP, tools & standards for ASIC/FPGA
FPGA chips database visualizer improvements
The F4PGA chip database visualizer helps the user with a visual representation of the underlying fabric. This visual feedback currently is limited to...
Verible SystemVerilog Preprocessor
The objective is to create a SystemVerilog preprocessor for Verible (which is a suite of SystemVerilog developer tools, including a parser,...
Creation of a cloud-based optimization infrastructure to test analog blocks in OpenFASOC
OpenFASOC is an open-source framework for autonomous generation of optimized integrated circuit blocks given user specifications. Most of the time,...
Development of a smart CI workflow to test analog block functionality and performance in OpenFASOC
OpenFASOC, an automated SOC generator, is enabling chip enthusiasts to develop circuits/macros with a software approach. Circuits must not only be...