This project aims to add support for the RISC-V Code size reduction extension (Zcb, Zcmp, Zcmt) to Rocket Core and perform the architectural testing...
DSP hard block integration in F4PGA
Abhishek_Anand
F4PGA is an open-source FPGA toolchain designed as a free alternative to proprietary computer-aided design tools like Xilinx’s Vivado. Currently,...
1st CLasS (Custom Logic as a Service) for Local FPGA Deployment using F4PGA
Ali Sajjad
1st CLasS framework is an open-source project that deals with the deployment of a custom kernel on AWS EC2 instance cloud FPGAs with fully automated...
Implementation of a Common Python Framework for OpenFASoC Generators
Harsh Khandeparkar
OpenFASoC is a project focused on creating fully automated user specifications to GDS generation flow using open-source tools. OpenFASoC uses tools...
Makerchip Flows: A Suite of EDA Flow integrations for TL-Verilog ecosystem
Shrihari
Makerchip Flows aims at developing EDA flows for TL-Verilog leveraging Edalize backend, for open source tools/flows like yosys, Openlane, F4PGA,...